Hardware Description Languages (HDLs), such as the Very high-speed integrated circuit Hardware Description Language (VHDL) or Verilog are text-based approaches to digital logic design through behavioral and/or structural description of design elements. HDL can be used to design: (1) a programmable logic device (PLD), such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD); (2) a mask programmable device, such as a hardwired programmable gate array (PGA), application-specific standard product (ASSP) or application specific integrated circuit (ASIC); (3) a system formed from selected electronic hardware components; or (4) any other electronic device. The HDL-based approach to design requires the user to describe the behavior of a system, which can then be simulated to determine whether the design will function as desired. The design is then synthesized to create a logical network list (“netlist”) that can be implemented within a particular device.
Many tools exist that allow electronic designs of integrated circuits (ICs) to be assembled, simulated, debugged, and translated into hardware. In general, an IC modeling system allows an IC design to be described and simulated with a gate-level abstraction. For example, a designer produces an electronic representation of the IC design using a modeling system by connecting and arranging schematic representations of circuit elements on a computer display, then uses the modeling system to translate the electronic IC design to a lower level HDL description, such as at a transistor or even lower level, for simulation or realization in hardware. For example, a simulator may accept transistor-level abstraction to simulate the electronic IC design, or place and route tools may accept a transistor-level HDL description of the electronic IC design to produce a configuration bitstream.
In some instances, an electronic IC design created within a modeling system must be tailored at a later stage of an overall design process. For example, a design developed within a modeling system may be tailored for incorporation within, or connection to, another IC design, most if not all of which is external to the modeling system. A modeling system may only support unidirectional ports, but incorporating the modeling system design in a larger design may require bidirectional ports. A modeling system may be used to process particular components of a circuit board, the remaining components being processed outside of the modeling system.
Conventionally, the results produced by a modeling system are tailored by hand, or by software that parses HDL. Tailoring by hand is tedious and error-prone, and HDL parsers are complicated and difficult to write. Furthermore, some of the information needed to tailor results (e.g., the date on which the design was produced, the collection of tools used to make the design, the names of the clock ports) may not be available in the HDL representation of the design produced by the modeling system.
Therefore, there exists a need in the art for an interface to an IC design produced by a modeling system. In particular, there exists a need for an interface that facilitates software modification of the IC design without requiring parsing an HDL representation.